8086 Microprocessor-Internal Architecture

Hello friends, today we are going to see the 8086 internal architecture. 8086 Microprocessor is a superset of 8085 microprocessor designed by Intel corporation in 1976.

8086 Microprocessor

The Intel 8086 is a 16-bit microprocessor intended to be used as the CPU in a microcomputer. The term “16-bit” means that its arithmetic logic unit, internal registers, and most of its instructions are designed to work 16-bit binary words. It has 16-bit data bus and 20-bit address bus. Words will be stored in two consecutive memory locations. If the first byte of a word is at an even address, the 8086 can read the entire word in one operation. If the first byte of the word is at an odd address, the 8086 will read the first byte in one operation, and the second byte in another operation. It consists of a powerful instruction set, which provides complicated operations like multiplication, division etc.

Features of Microprocessor

There are different types of features in 8086 microprocessor, These are as follows ...

1. It is a 16-bit Microprocessor.

2. 8086 has a 20 bit address bus that can access up to 220 = 1 MB memory locations.

3. 8086 has a 16 bit data bus. It can read or write data to a memory/port either 16 bits or 8 bit at a time.

4. It can support 64 K I/O ports.
The frequency range of 8086 is 6-10 MHz

5. It has multiplexed address and data bus AD0- AD15 and A16 – A19.

6. It can pre-fetch up to 6 instruction bytes from memory and queues them in order to speed up instruction execution.

7. It requires +5V power supply.

8. A 40 pin dual inline package. 8086 is designed to operate in two modes, Minimum mode and Maximum mode.

The minimum mode is selected by applying logic 1 to the MN/MX input pin. This is a single microprocessor configuration. 

The maximum mode is selected by applying logic 0 to the MN/ MX input pin. This is a multi microprocessors configuration.

Internal Structure of 8086

Microprocessor The following figure shows the internal block diagram of the 8086 microprocessor.

Internet architecture of 8086 microprocessor

Functional Parts of 8086

The 8086 CPU is divided into two independent functional parts, the bus interface unit or BIU, and the execution unit or EU.

The Bus Interface Unit

The BIU handles all data and addresses on the buses for the execution unit such as it sends out addresses, fetches instructions from memory, reads data from ports and memory as well as writes data to ports and memory. In BIU there are so many functional groups or parts these are as follows.

Instruction Queue

To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from memory. The prefetched instruction bytes are held for the EU in a first in first out group of registers called an instruction queue. When the EU is ready for its next instruction, it simply reads the instruction from this instruction queue. This is much faster than sending out an address to the system memory and to send back the next instruction byte. Fetching the next instruction while the current instruction executes is called pipelining.

Segment Registers

The BIU contains four 16-bit segment registers. They are the extra segment (ES) register, the code segment (CS) registers, the data segment (DS) registers, and the stack segment (SS) registers. These segment registers are used to hold the upper 16 bits of the starting address for each of the segments. The part of a segment starting address stored in a segment register is often called the segment base.

1. Code Segment (CS): 

The CS register is used for addressing a memory location in the Code Segment of the memory, where the executable program is stored.

2. Data Segment (DS):

The DS contains most data used by a program. Data are accessed in the
Data Segment by an offset address or the content of other registers that holds the offset address.

3. Stack Segment (SS):

SS defined a section of memory to store addresses and data while a subprogram executes.

4. Extra Segment (ES):

ES is an additional data segment that is used by some of the string to hold the extra destination data.

8086 Memory Segment

Instruction Pointer (IP)

In the BIU, the next register, below the segment register is the instruction pointer. The instruction pointer (IP) holds the 16-bit address of the next code byte within this code segment.

The Execution Unit

The execution unit (EU) tells the BIU where to fetch instructions or data from, decodes instructions, and executes instructions.

The functional parts of the execution unit are control circuitry or system, instruction decoder, and Arithmetic logic unit (ALU).

Control circuitry to perform various internal operations. A decoder in the EU translates instructions fetched from memory to generate different internal or external control signals that required performing the operation. The EU has a 16-bit ALU, which can perform arithmetic operations such as add, subtract etc. and logical operations such as AND, OR, XOR, increment, decrement etc.

Flag Register

A 16-bit flag register is a flip-flop that indicates some condition produced by the execution of an instruction or controls certain operations of the EU. They are modified automatically by the CPU after mathematical operations. It has 9 flags and they are divided into two categories:

1. Conditional Flags

2. Control Flags

Conditional Flags:

Conditional flags represent the result of the last arithmetic or logical instructions.

· Carry Flag (CF): This flag will be set to one if the arithmetic operation produces the carry in MSB position. It is also used in multiple-precision arithmetic.

· Auxiliary Flag (AF): If an operation performed in ALU generates a carry/borrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag; it is used internally by the processor to perform Binary to BCD conversion.

· Parity Flag (PF): This flag is used to indicate the parity of the result. If lower order 8-bits of the result contains an even number of 1’s, the Parity Flag is set to one and for an odd number of 1’s, the Parity Flag is reset i.e. zero.

· Zero Flag (ZF): It is set to one; if the result of an arithmetic or logical operation is zero else it is reset.

· Sign Flag (SF): In sign-magnitude format, the sign of the number is indicated by MSB bit. If the result of the operation is negative, the sign flag is set to one.

· Overflow Flag (OF):

It occurs when signed numbers are added or subtracted. An OF indicates that the result has exceeded the capacity of the machine.

Control Flags 

Control flags are intentionally set or reset to control certain operations of the processor with specific instructions put in the program from the user. Control

flags are as follows:

1. Trap Flag (TP): It is used for single-step control. It allows user to execute one instruction of a program at a time for debugging. When the trap flag is set, the program can be run in single-step mode.

2. Interrupt Flag (IF): It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of a program. If it is set, the maskable interrupt is enabled and if it is reset, the interrupt is disabled.

3. Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from higher memory address to lower memory address. When it is reset, the string bytes are accessed from the lower memory address to the higher memory address.

8086 Flag Register Format

General Purpose Registers

The EU has eight general-purpose registers labelled AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be used individually for the temporary storage of 8-bit data. The AL register is also called the accumulator. Certain pairs of these general-purpose registers can be used together to store 16-bit data. The valid register pairs are AH and AL, BH and BL, CH and CL and DH and DL. These register pairs are referred to as the AX, BX, CX, and DX resp.

AX Register: For 16-bit operations, AX is called the accumulator register that stores operands for arithmetic operations.

BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment.

CX Register: It is defined as a counter. It is primarily used in loop instruction to store the loop counter.

DX Register: DX register is used to contain the I/O port address for I/O instruction.

Stack Pointer Register:

The stack pointer (SP) register contains the 16-bit offset from the start of the segment to the memory location where a word was most recently stored on the stack. The memory location where a word was most recently stored is called the top of the stack.

Other Pointer and Index Registers

The EU also contains a 16-bit source index (SI) register, base pointer (BP) registers, and Destination Index (DI) registers. These three registers can be mainly used for the temporary storage of 16-bit data just like a general-purpose register.

Difference between 8085  and 8086 Microprocessor

When we compare two products mainly we are considering following points.

Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.

Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.

Data Bus -- 8085 has 8-bit  Dara bus where as 8086 has 16-bit data Bus.

Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.

I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's.

Cost − The cost of 8085 is low whereas that of 8086 is high

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