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80186 Microprocessors: Introduction and Architecture

Hello friends, today we are going to discuss the 80186 microprocessor with integrated peripherals. The Intel 80186 is an improved version of the 8086 microprocessor. 80186 is a 16-bit microprocessor with a 16-bit data bus and a 20-bit address bus. It has a programmable peripheral device integrated into the same package. The instruction set of the 80186 is a superset of the instruction set of the 8086. The term super-set means that all of the 8086 instructions will execute properly on an 80186, but the 80186 has a few additional instructions. The following figure shows the block diagram and pin diagram of 80186. The CPU is divided into seven independent functional parts. 80186 internal block diagram  80186 68-pins pin diagram  Functional parts of 80186 Microprocessor The Bus Interface Unit (BIU) Execution Unit (EU) Clock Generator Programmable interrupt controller Programmable Chip Select Unit (CSU) Programmable DMA Unit Programmable counter/timers The Bus Interface Unit

Data Transmission in OSI Model

Hello friends, in the previous post we have seen the detail architecture of OSI reference model, now we will see how data can be transmitted in the OSI model. Following fig. shows an example of data transmission in OSI model.

data transmission in OSI reference model
data transmission in OSI reference model

Fig. An example of how the OSI model is used.

The sending process has some data to send the receiving process. It gives the data to the application layer, which then attaches the application header, AH (Which may be null), and gives the resulting item to the presentation layer.
The presentation layer may transform this item in various ways and possibly add a header to the front, and send to the session layer.
This process is repeated until the data reach the physical layer, where they are actually transmitted to the receiving machine.
On that machine the various headers are stripped off one by one as the message propagates up the layers until it finally arrives at the receiving process.
The key idea throughout is that the actual data transmission is vertically not in horizontal manner i.e. not direct transmission takes place through transport layer of source machine to transport layer of destination machine.

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